Business Unit — ASIC Design

ASIC Design

Complete Flow from RTL to Tapeout

Team with proven track record in ASICs from 100G to 400G — 28nm → 12nm → 7nm → 6nm FinFET. The most advanced ASIC developed in Brazil: 1B+ transistors.

1B+
Transistors
6nm
FinFET
22+
ASIC Team
400Gbps
Coherent communications

Understand the Technology

What is an ASIC?

ASIC stands for Application-Specific Integrated Circuit — a chip designed from scratch to perform one specific function with maximum efficiency. Unlike a general-purpose processor that does everything reasonably well, an ASIC does one thing extraordinarily well.

Conceptual layout of a 6nm ASIC for 400G/800G coherent optical networks — functional blocks: SerDes, DSP Core, SRAM, Analog, Control Logic, and Network Interface

ASIC vs CPU: what's the difference?

Imagine you need to slice bread. A chef's knife works — but a professional bread slicer is incomparably faster, more precise, and more efficient. Your computer's CPU is the chef's knife: versatile, but generic. The ASIC is the slicer: built for one purpose, unbeatable at it.

In practice, an ASIC for 400G/800G optical networks processes digital signals at speeds no conventional processor could match — with 10× lower power consumption and in a chip the size of a fingernail. It's the heart of the routers and transponders that move the global internet.

Where are ASICs in the real world?

  • Telecom networks: 400G/800G transponders that carry all internet traffic between continents and data centers.
  • Artificial Intelligence: GPUs and TPUs — like those from NVIDIA and Google — are ASICs optimized for neural network matrix multiplication.
  • Smartphones: the camera chip, 5G modem, and security processor are all different ASICs inside your phone.
  • Scientific instrumentation: CERN detectors, space telescopes, and medical CT scanners use custom ASICs to process signals in real time.

RTL Design

Everything starts with code. Engineers describe chip behavior in languages like SystemVerilog — the "software" that becomes hardware.

Synthesis & Place-and-Route

The code is converted into billions of transistors positioned nanometrically on silicon. A process with over 50 EDA steps.

Fabrication (Tapeout)

The final GDSII goes to the foundry (e.g., TSMC 6nm). Hundreds of lithographic steps etch the patterns into silicon with atomic precision.

Silicon Validation

The first physical chip is tested and validated. HwIT takes chips from RTL to functional silicon with a proven track record from 28nm to 6nm.

Complete Process

RTL-to-Silicon Flow

Complete flow, from specification to GDSII — architecture, frontend, backend, analog, DFT and silicon validation.

Silicon Validation
Custom EVBs + Full Characterization
Custom validation boards, S-parameter measurement, eye diagrams, field testing and silicon-to-RTL bug traceability.
Advanced Packaging
Experience with SWIFT™ Fan-Out (Amkor)
12×12 mm package, 868 BGA balls. Chiplet integration and multi-die co-design for next-generation ASICs.
Tapeout History

Tapeout Track Record

10 years of technological evolution — from ISDB-T in 65nm to 400G coherent DSP in 6nm FinFET.

2012
65nm
ISDB-T Digital TV
2017
28nm
100G DSP
2020
7nm
400G DSP
2022
6nm
400ZR+
Project Technology Tapeout Transistors Application
Digital TV Demodulator 65nm 2012 — ISDB-T (Brazilian digital TV)
100G Coherent DSP 28nm Dec/2017 400M+ DP-QPSK, 100GbE/OTN, 2000 km
400G Coherent DSP 7nm FinFET Jan/2020 1B+ 400ZR DCI
400ZR+ 6nm FinFET 2022 — Advanced multi-modulation
Technical Highlight

7nm ASIC — 400G Coherent DSP

One of the most advanced chips developed in Brazil — DSP-ASIC for 400G coherent optical communications, manufactured at TSMC in 7nm FinFET.

Die Specifications
Standard OIF-400ZR-01.0
Modulation 60 GBd DP-16QAM
Capacity 400 Gbps
Die size 6.3 × 4.2 mm
Transistors 1B+
Process TSMC 7nm FinFET
Package SWIFT™ (Amkor)
Package size 12 × 12 mm
BGA Balls 868
Line Interface
4 × 90
GSa/s ADC/DAC
60 GBd
Symbol Rate
DP-16QAM
Modulation
FEC
Integrated SD-FEC
Host Interface
8 × 56
Gb/s CEI VSR
400G
AUI-8
8 × 63.5
MHz HOST DAC
OIF
400ZR-01.0
Brazil
The most advanced ASIC ever developed in the country
Capabilities by Phase

Accumulated Technical Expertise

Expertise built over 15 years across every phase of the high-speed ASIC design flow.

Phase Expertise
System & Algorithm Design MATLAB/Python modeling, coherent DSP, FEC, 4/8/16QAM modulations, equalization
RTL Design & Verification SystemVerilog/SystemC, UVM, coverage-driven verification, formal verification
Synthesis & DFT Technology-agnostic, scan chains, BIST, SDC constraints, power intent (UPF)
Physical Design Floorplan, CTS, routing, timing signoff, power analysis, ECO flow
Analog Design ADC/DAC, PLLs, PVT sensors, CDR — digital/analog co-design in advanced nodes
Silicon Validation Custom EVBs, S-parameters, eye diagrams, field testing, silicon debug
Advanced Packaging SWIFT fan-out, multi-die, chiplet integration — Amkor TSMC advanced packaging
Team

ASIC Team

22 specialized engineers with access to advanced technology PDKs — TSMC 7nm and 6nm FinFET.

22+
ASIC Engineers
Specialized in digital, analog and mixed-signal chip design
15+
Years of Experience
Senior members with background at IPG Photonics, Lumentum, BrPhotonics
4
Tapeouts Completed
65nm → 28nm → 7nm → 6nm — continuous node advancement
Access to Advanced Technologies
TSMC 7nm FinFET — full PDK
TSMC 6nm FinFET — full PDK
Full EDA flow (Synopsys/Cadence)
SWIFT Package (Amkor) — fan-out wafer-level
Engagement Models

ASIC Services for Clients

Flexible engagement — from full RTL-to-Silicon to IP core delivery or silicon validation.

Full ASIC Development

From spec to tapeout — architecture, FE, BE, Analog, DFT and full silicon validation.

ArchitectureRTLPhysicalAnalogSilicon Val.

IP Core Delivery

Delivery of verified RTL block: DSP cores, FEC, SerDes, CDR — ready for integration.

Verified RTLUVMTiming/Power

Physical Design

Floorplan, P&R and Signoff for clients with validated frontend. Guaranteed timing closure.

FloorplanP&RTiming Signoff

Silicon Validation

EVB design + full chip characterization after tapeout. Silicon debug through to product.

EVB DesignS-paramsEye Diagrams

FPGA Prototyping

FPGA prototyping before tapeout — risk reduction and early architecture validation.

XilinxIntelRisk Reduction

Analog Design

ADC/DAC, PLLs, PVT sensors, CDR and analog blocks in advanced nodes up to 6nm.

ADC/DACPLLCDRPVT

Have an ASIC project?

Our team evaluates technical feasibility with no commitment —
from spec to tapeout in 6nm FinFET.

Request Project Assessment View R&D Photonics

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